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L6238S 12v sensorless spindle motor controller product preview 12v operation 3a, three-phase dmos output (total r dson 0.52 w ) no hall sensors required digital bemf processing linear or pwm control stand alone or ext. driver shoot-through protection thermal shutdown description the L6238S is a three-phase, d.c. brushless spindle motor driver system. this device features both the power and sequence sections. higher power applications can be activied with the addition of an external linear driver, or by op- erating the internal drivers in pwm. motor start-up, without the use of hall sensors, can be achieved either by an internal start-up al- gorithm or by manually sequencing the output drivers, using a variety of user-defined start-up algorithms. protection features include stuck rotor\backward rotation detection and automatic thermal shut- down. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. october 1995 zero crossing detector align + go start-up one-shot slew-ctrl pwm lin vl thermal shutdowm ot-warn charge pump cpump3 cpump1 cpump2 d95in232 bias power stage av=4v/v digital delay out b out c ctr tap csa input gnd pwm tim vanalog + + + - bemf sense vpower brake delay rsense1 drv cntl tdly(0) + - csa out a gate drive gm comp system clock sys clock rsense2 vctrl pwm comp pwm/ slew sequencer falign output enable run/ brake seq incr mono/seq ctrl tdly(1) tdly(2) mono det mask dly toggle divide by n spin sense fmtr sel pol block diagram ordering numbers: L6238S (plcc44) L6238Sqa (pqfp44) L6238Sqt (tqfp64) plcc44 pqfp44 tqfp64 1/31
absolute maximum ratings symbol parameter value unit bv dss output brakdown voltage 17 v v power motor supply voltage 15 v v logic logic supply voltage 7 v v analog analog supply voltage 15 v v in input voltage -0.3 to 7 v c storage charge pump storage capacitor 4.7 m f i mdc motor current (dc) (tqfp64 only) (plcc44 and pqfp44) 3 2.5 a a i mpk peak motor current (pulsed: t on = 5ms, d.c. = 10%) 5 a p tot power dissipation at tamb = 50 c (plcc44) (tqfp64) (pqfp44) 2.3 1.7 1.3 w w w ts storage and junction temperature -40 to 150 c thermal data symbol parameter plcc44 pqfp44 tqfp64 unit r th (j-amb) thermal resistance junction-ambient 34 45 45 c/w those thermal data are valid if the package is mounted on mlayer board in stillair 1 2 3 5 64 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 34 35 33 32 31 30 29 40 41 42 44 43 23 22 21 19 18 20 28 27 26 24 25 output b spin sense brake delay charge pump 2 gnd rsense 1 gnd mask delay vpower pwm/slew center tap gnd charge pump 1 charge pump 3 output a vanalog vpower n.c. tdly(0) tdly(1) tdly(2) gnd gnd gate drive gm comp output c csa input rsense 2 vcontrol n.c. fmotor vlogic gnd run/brake output enable pwm/linear select pole otwarn pwm limit tmr pwm comp falign mono/seqinc ctrl seq. increment system clock d95in245 pin connection plcc44 (top view) L6238S 2/31
1 2 3 5 64 7 8 9 10 24 11 25 26 27 28 29 62 61 60 59 57 58 56 55 54 53 52 43 42 41 39 38 40 48 47 46 44 45 output a output a n.c. vpower vanalog vpower gnd gnd gnd charge pump 3 charge pump 1 n.c. otwarn select pole pwm limit tmr output enable pwm/linear run/brake seq. increment system clock mono/seqinc ctrl falign charge pump 2 rsense 1 rsense 1 brake delay output b spin sense output b pwm/slew center tap vpower vpower output c output c n.c. rsense 2 csa input rsense 2 gnd gnd gnd gm comp gate drive d95in244 19 20 21 22 23 30 31 32 51 50 49 pwm comp n.c. gnd mask delay gnd gnd 64 63 gnd n.c. gnd gnd 17 18 12 13 14 15 16 37 36 34 33 35 tdly(0) tdly(1) gnd gnd tdly(2) vcontrol fmotor gnd gnd vlogic pin connection tqfp64 (top view) 1 2 3 5 64 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 vanalog n.c. tdly(0) tdly(2) gnd tdly(1) gnd charge pump 1 charge pump 3 vpower output a otwarn select pole pwm limit timer pwm/linear run/brake output enable seq. increment system clock mono/seqinc ctrl faling pwm comp. gnd charge pump 2 rsense 1 brake delay output b spin sense pwm/slew center tap vpower mask/delay gnd csa input vcontrol n.c. vlogic gnd fmotor gnd gate drive gm comp rsense 2 output c d95in243 12 13 14 15 16 pin connection pqfp44 (10x10) (top view) L6238S 3/31
pin functions plcc44 pqfp44 tqfp64 name i/o function 1 39 56, 57 output b i/o dmos half bridge output and input b for bemf sensing. 2 40 58 spin sense o toggless at each zero crossing of the bemf. 3 41 59 brake delay i energy recovery time constant, defined by external r-c to ground. 4 42 60, 61 r sense 1 o outputs a+b connections for the motor current sense resistor to ground 5 43 62 charge pump 2 i negative terminal of pump capacitor. 6, 7, 17, 29, 39, 40 1, 11, 23, 33, 34, 44 * ground s ground terminals. 8 2 4 charge pump 1 i positive terminal of pump capacitor. 9 3 5 charge pump 3 o positive terminal of storage capacitor. 10 4 6, 7 output a i/o dmos half bridge output and input a for bemf sensing. 11, 42 5, 36 9, 10, 52, 53 v power s power section supply terminal. 12 6 11 v analog s 12v supply. 13, 32 7, 26 8, 18, 19, 31, 41 n.c n.c open terminal 14 8 12 tdly(0) i three bits that set the delay between the detection of the bemf zero crossing, and the commutation of the next phase. 15 9 13 tdly(1) i 16 10 14 tdly(2) i 18 12 20 otwarn o overtemperature warning output 19 13 21 select pole i selects # of motor poles. a zero selects 8, while a one selects 4 poles. 20 14 22 pwm timer i capacitor connected to this pin sets the maximum time allowed for 100% duty cycle during pwm operation 21 15 23 pwm/linear i selects pwm or linear output current control 22 16 24 output enable i tristates power output stage when a logic zero. 23 17 25 sequence i rising edge will initiate start-up. a braking rountine is started when this input is brought low. 24 18 26 seq increment i a low to high transition on this pin increments the output state sequencer. 25 19 27 system clk i clock frequency for the system timer/counters. 26 20 28 mono/seq. inc. control i a logic one will disable the monotonicity detector and sequence increment functions. 27 21 29 falign i reference frequency for the opt. auto-start algorithm. if int. start up is not used, this pin must be connected to the system clock. 28 22 30 pwm comp o output of the pwm comparator 30 24 35 vlogic s 5v logic supply voltage. 31 25 36 fmotor o motor once-per-revolution signal. 33 27 37 vcontrol i voltage at this input controls he motor current 34 28 38 csa input i input to the current sense amplifier. 35 29 39, 40 rsense 2 o output c connection for the motor current sense resistor to ground. 36 30 42, 43 output c i/o dmos half bridge output and input c for bemf sensing. 37 31 44 gm comp i a series rc network to ground that defines the compensation of the transconductance loop. L6238S 4/31
pin functions plcc44 pqfp44 tqfp64 name i/o function 38 32 45 gate driver i/o drivers the ext. pfet gate driver for higher power applications. this pin must be grounded if an external driver is not used. 41 35 51 mask/delay o internal logic signals used for production testing 43 37 54 center tap i motor center tap used for differential bemf sensing. 44 38 55 pwm/slew i r/c at this input set the linear slew rate and pwm off-time 0.0 0.3 1.0 3.0 cb( m f) 0.0 0.3 1.0 3.0 t bd (s) d95in274 figure 1: brake delay timeout vs c brake (r brake = 1meg) 10 30 100 300 rs(k w ) 0.0 0.3 1.0 3.0 s vr (v/ m s) d95in275 figure 2: linear slew rate vs r slew 100 300 coff(pf) 1 3 10 30 pwm ( m s) d95in276 figure 3: pwm off - time vs r slew /c off 100 300 ctimer(pf) 10 30 pwm ( m s) d95in277 figure 4: pwm limit time - out vs c timer L6238S 5/31
electrical characteristics (t amb =0to70 c; v a =v pwr = 12v; v logic = 5v; unless otherwise specified) symbol parameter test condition min. typ. max. unit general v analog analog supply voltage 10.5 13.5 v i analog analog supply current run mode v a = 13.5v 1.5 2.7 4.5 ma brake mode v a = 13.5v 280 800 m a v logic logic supply voltage 4.5 5.0 5.5 v i log ic logic supply current run mode v logic = 5.5v 1 2 3.2 ma brake mode 100 500 1000 m a thermal shutdown *t sd shut down temperature 150 180 c *t hys recovery temperature hysteresis 30 c *t ew early warning temperature t sd -25 c power stage r ds(on) output on resistance per fet t j =25 c; v a = 10.5v t j = 125 c; v a = 10.5v 0.20 0.26 0.40 w w i o(leak) output leakage current v pwr = 15v 1 ma v f body diode forward drop i m = 2.0a 1.5 v dvo/dt output slew rate (linear) r slew = 100k w 0.15 0.30 0.45 v/ m s output slew rate (pwm) 10 150 v/ m s i gt gate drive for ext. power dmos v control = 1v; v sns = 0v; v a = 10.5v 4.5 ma v gate-drive ext driver disable voltage 0.7 v v ctrl-range voltage control input range 0 5.0 v i in(vctrl) voltage control input current 10 m a pwm off-time controller (r slew = 100k w ,c off = 120pf) t off off time 9 11 14 m s v chrg capacitor charge voltage v a = 10.5v 2.31 2.65 3.1 v v trip lower trip threshold 1.25 v pwm limit timer i chrg capacitor charge current v pwm timer = 0v; v a = 10.5v 10.0 20.0 30 m a v chrg capacitor charge voltage v a = 10.5v 3.0 3.5 4.0 mv v trip lower trip threshold 100 400 v bemf amplifier z inct center tap imput impedance 20 30 40 k w v bemf minimum bemf (pk-pk) 60 mv current sense amplifier i snsin input bias current v a = 13.5v 10 m a g v voltage gain 3.8 4.0 4.2 v/v sr slew rate 0.33 0.8 v/ m s L6238S 6/31
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit brake delay v chrg capacitor charge voltage r t = 50k 8.8 9.6 10.5 v i in input current v in = 5.0v 500 na i out3 source current v a = 10.5v 0.5 ma v thres delay timer low trip threshold 1.2 1.8 2.8 v charge pump v out storage capacitor output voltage v a = 10.5v; i out = 500 m a17 v f cp charge pump frequency 140 450 khz i in vstorage input current (run mode) v storage = 12v; v a =v logic =0 25 m a i brkdly vstorage leakage current (brake delay mode) v storage = 12v; v a =v logic = 0 0.4 1 m a i brake vstorage leakage current (brake mode) v storage = 12v; v a =v logic = 0 0.1 1 m a sequence increment t seq time between rising edges 1 m s output transconductance amplifier note: measure at ota comp. pin. v oh voltage output high v a = 10.5v 10 v v outl output voltage 2.0 v i source output voltage 40.0 0.5 v i sink output sink current 40.0 m a logic section v inh v inl input voltage (all inputs except run/brake v logic = 4.5 to 5.5v 3.5 1.5 v v v inh v inl run/brake input voltage v logic = 4.5 to 5.5v 2.0 1.0 v v i inh i inl input current -1.0 1.0 m a ma v outl v inl output voltage vsink = 2.0ma v source = 2.0ma 4.5 0.5 v v f sys system clock frequency 8.0 12.0 mhz t off /t on clock on/off time 20 ns tdelay (2) tdelay (1) tdelay (0) commutation phase delay, in electrical degrees 1 0 1 2.0 1 0 0 9.4 1 1 1 18.80 1 1 0 20.68 0 0 1 22.56 0 0 0 24,44 (*) 0 1 1 26.32 0 1 0 28.20 (*) input default phase delay truth table L6238S 7/31
functional description 1.0 introduction 1.1 typical application in a typical application, the L6238S will operate in conjunction with the l6244 voice coil driver as shown in fig. 1-1. this configuration requires a minimum amount of external components. 1.2 input default states figure 1-2 depicts the two possible input struc- tures for the logic inputs. if a particular pin is not out a 10 ctr tap 43 out b 1 out c 36 rsense 4.35 csa 34 6.33 10nf 5 8 chrg pump 2 chrg pump 1 8.12mhz 4.7 m f 25 9 chrg pump 3 sys clk 22 m f f align v pwr 27 11,42 400pf 44 pwm slew 100k 10k 37 0.068 m f gm comp 0.1 m f 3 brk dly 6,7,17, 29,39,40 gnd 60-90hz note: if the internal start-up algorithm is not used, connect this pin to sys_clk v anlg 12v v logic vlogic(5v) 12 39 L6238S spindle motor driver controller 220pf 20 16 15 14 18 31 34 33 23 22 38 26 gate drv mono seq. out ena run/brk v ctrl seq inc f mtr ot warm t dly(0) t dly(1) t dly(2) pwm tmr 19 data(0) 20 data(1) 21 data(2) 22 data(3) 23 data(4) 24 data(5) 25 data(6) 26 data(7) 36 wr 28 a0 27 a1 18 cs 43 35 10k v logic por 44 9 37 gate drive 42 vpower 1 m f 0.068 m f 3.6k 27k 0.1 m f vcm rs 0.4 38 4 5 8 360k 12 360k 13 360k 14 10k 11 100k 10 15 6,7,17,29,39,40 41 314 31 33 gnd por dly rprogram v prog v cc/2 gain2-in da0out gain1-in error amp output v pump cp2 cp1 0.01 m f d95in278 l6244 voice coil driver da2 out sense out out b sense +input sense -input out a v cc sense figure 1-1 L6238S 8/31
used in an application, it may either be connected to ground or vlogic as required, it may also be simply left unconnected. if no connection is made, the pin is either pulled high or low by internal constant current gener- ators as shown above. a listing of the logic and clock inputs is shown in table 1 with the corresponding default state. 1.3 modes of operation there are 5 basic modes of operation. 1) tristate when output enable is low, the output power drivers are tristated. 2) start-up with output enable high, bringing run/brake from a low to a high will energize the motor and the system will be driven by the fully-integrated startup algorithm. a user-defined start-up algorithm, under control of a microprocessor, can also be achieved via the sequence increment input. 3) run run mode is achieved when the motor speed (controlled by the external microprocessor) reaches the nominal speed. 4) park when run/brake is brought low, energy to park the heads may be derived from the rectified bemf. the energy recovery time is a function of the brake delay time constant. in this state, the qui- escent current of the device is minimized (sleep mode). 5) brake after the energy recovery time-out, the device is in brake, with all lower drivers in full conduc- tion. there are two mutually exclusive conditions which may be present during the tristate mode (wake up): a)the spindle is stopped. b)the system is still running at a speed that allows for resynchronization. in order to minimize the ramp up time, the micro- controller has the possibility to: check the spin sense pin, (which toggles at the bemf zero crossing frequency) enable the power to the motor based on the previous information. otherwise the m p may is- sue a brake command, followed by the start- up procedure after the motor has stopped spin- ning. 2.0 state diagrams 2.1 state diagram figure 2-1 is a complete state diagram of the controller depicting the operational flow as a func- tion of the control pins and motor status. the flow can be separated into four distinct operations. 2.2 align + go figure 2-2 represent the normal flow that will achieve a spin-up of the spindle motor using the internally generated start up algorithm. upon power up, or from any state with run/brake low the controller first sets the state machine for state=1 with the outputs tristated. the period counter that monitors the time be- tween zero crossing is stopped, analog with the phase and mask delay counters. when run/brake is brought high, the motor is in the first part of the align mode at state 2 (output a high and output c low). if output enable is high, the controller first checks to determine if the motor is still spinning for a time of 21 w (with sys_clk = 10mhz). the drivers are now enabled and after the align time-out, (64/falign), the se- quencer double increments the outputs to state 4 (output b high and output a low). the first part of this align mode is used to reduce the effects of stiction pin function configuration tdly (0,1,2) pull-down select pole pull-down pwm/linear pull-down output enable pull-down run/brake pull-up sequence increment pull-down system clock pull-up faling pull-up table 1 330 v logic 10 m a 330 v logic 10 m a pull-up pull-down d95in279 figure 1-2 L6238S 9/31
after the next align time-out 192/falign), the con- troller enters the go mode, were the sequencer again double increments the output phase upon detection of the motor's bemf. the align time-out may be optimized for the appli- cation by changing the faling reference fre- quency. a watch-dog timer protection feature is built into the control logic to monitor the falign pin for a clocking signal. this circuitry, shown in figure 2-3 will prevent start up the device if the falign clock is not present. without this feature, the output would remain in the first phase under high current conditions, if the clock were not present. if the external sequencer is used to provide start up, the system clock may be tied to the falign pin to satisfy the requirements of the watch-dog timer. 2.3 resynchronization if power is momentarily lost, the sequencer can automatically resynchronize to the monitored state = 1 drivers off min clock delay period stop delay stop mask stop seqlnc=1 & outena=0 run/brk=x int. start-up disabled min. clock delay load min. delay load min. mask*** run/brk=1 & outena=1 drivers on period count delay count state=state+1* mask count mask count seqinc=0 seqinc=1 load delay=period load mask=period reset period period count delay count** bemf bemf seqinc=0 seqinc=1 run/brake=1 run/brake=0 from any state drivers off min clock delay load min mask*** period stop delay count state=state+1 mask count load min. delay load min. mask*** delay count state=state+1 mask count bemf state=state+1 seqinc=1 return to previous state (changing seqinc=1) bemf from any state with seq_inc=0 * valid if seqinc=0, and delay times out ** clock delay=f(tdly_[2:0]) when bemf period <3.3ms @ 10mhz (speed >12.7hz for 8 poles) state=state+2 check for zc bemf drivers off state=state+1 min clock delay load min delay load max mask delay count state=state+1 mask count outena=1 outena=1 outena=1 drivers off min clock delay period stop drivers on period stop delay stop mask stop state=state+2 state=state+1 load delay=min load mask=max period count delay count state=state+1 mask count bemf load delay=min load mask=min reset period period count delay count* state=state+1 mask count 2 21 sys_clk 2 21 sys_clk drivers off run/brk=0 drivers off run/brk=0 drivers on load delay=period load mask=period reset period period count delay count* state=state+1 mask count drivers off min clock delay period stop outena=0 bemf mono=0** bemf outena=1 outena=1 bemf align & go mode resynchronization mode run mode * clock delay=f(tdly [2:0] when bemf period <3.3ms @ 10mhz (speed>12.7hz for 8 poles) bemf: bemf rising with pnslope=1 or bemf falling with pnslope=0 bemf1: bemf rising with pnslope=0 or bemf falling with pnslope=1 **mono=0 when freq(bemf)=2*freq(phase) ***min mask=192/sys_clk(i.e. with sys_clk=10mhz,min mask=19.2 m s) d95in280 192/falign 64/falign outena=0 2 21 sys_clk outena=0 outena=1 bemf por=0 from any state (for is generated internally by monitoring vlogic) figure 2-1 L6238S 10/31
bemf. this resychronization can either occur whenever output enable or run/brake is first brought low then high. referring to figure 2-4, the ohold for resynco state is brought low. the controller leaves this state and enters ostart resynco when output en- able is high. s q q to start-up logic s over temp shutdown d95in311 output enable run/ brake falign figure 2.3: watch-dog timer load min delay load min mask*** delay count state=state+1 mask count load delay=min load mask=min period count delay count* state=state+1 mask count check for zc outena=1 bemf drivers off min clock delay period stop d95in312 *clock delay=(tdly [2:0] when bemf period <3.3ms @ 10mhz (speed>12.7hz for 8 poles) bemf: bemf rising with pnslope=1 or bemf falling with pnslope=0 bemf: bemf rising with pnslope=0 or bemf falling with pnslope=1 ** mono=0 when freq (bemf)=2*freq(phase) *** min mask=192/sys_clk(i.e.with sys_clk=10mhz, min mask=19.2 m s) bemf run/brk=0 bemf bemf drivers off drivers on load delay=period load mask=period reset period period count delayh count* state=state+1 mask count mono=0** bemf bemf run mode outena=0 outena=1 hold for resync resynchronization mode figure 2-4 state=1 drivers off min clock delay period stop delay stop mask stop drivers off min clock delay load min delay load min mask period stop delay count state=state+1 mask count check for zc drivers on period stop delay stop mask stop state=state+1 load delay=min load mask=max period count delay count state=state+1 mask count check for zc bemf 2 21 sys_clk run/brake=1 por=0 from any state outena=1 64/falign 192/falign drivers on load delay=period load mask=period reset period period count delay count* state=state+1 mask count bemf d95in310 bemf: bemf rising with pnslope=1 or bemf falling with pnslope=0 bemf: bemf rising with pnslope=0 or bemf falling with pnslope=1 ***min mask=192/sys_clk (i.e. with sys_clk=10mhz, min mask=19.2 m s) bemf run/brk=0 from any state figure 2.2 L6238S 11/31
if zero crossings are detected, the sequencer will automatically lock on to the proper phase. this resynchronization will take effect with the motor speed running as low as typically 30% of it's nominal value. 2.5 external sequencing although the user-defined start-up algorithm is flexible and will consistently spin up a motor with no external interaction, the possibility exists where certain applications might require complete microprocessor control of start-up. the L6238S offers this capability via the se- quence increment input. referring to figure 2-5, during initial power-up with output enable low, the controller is in the ohold and wait for de- cisiono state. if the sequence increment pin is brought high during this state, the auto startup algorithm is disabled and the sequencer can be controlled externally. when output enable and run/brake are brought high, the sequencer is incremented on each positive transition o the sequencer in- crement pin. during the time that this pin is high, all bemf information is masked out. when it is low, the bemf information can be detected nor- mally after the internal mask time. the minimum mask time is 192/sys_clk (i.e. with sys_clk = 10mhz, min. mask = 19.2 m s) therefore to insure that the sequencer is under complete control of the state machine, the time that the sequence increment pin is held low should be much less then the min. mask time, but greater then 1 m s. when the motor has reached a predetermined speed, the sequence increment pin can be left low and the L6238S motor control logic will take over and automatically spin up the motor to the desired speed . 3.0 start-up algorithms 3.1 spin-up operation the spin operation can be separated into 3 parts: 1) open loop start-up - the object is to create motion in the desired direction so that the bemf voltages at the 3 motor terminals can provide reli- able information enabling a transition to closed loop operation. state=1 drivers off min clock delay period stop delay stop mask stop int start-up disabled min clock delay load min delay load min mask mask count seqinc=1 & outena=0 run/brk=x d95in313 *valid if seqinc=0, and delay times out **clock delay=f(tdly_[2:0]) when bemf period <3.3ms @ 10mhz (speed >12.7hz for 8 poles) seqinc=0 state=state+1 mask count load delay=period load mask=period reset period period count delay count** bemf por=0 from any state drivers on period count delay count seqinc=0 bemf seqinc=1 state=state+1 seqinc=1 from any state with seq_inc=0 return to previous state (changing seqinc=1) run/brk=1 & outena=1 seqinc=1 figure 2-5 L6238S 12/31
2) closed loop start-up - the bemf voltage zerocrossings provide timing information so that the motor can be accelerated to steady state speed. 3) steady-state operation - the bemf voltage zero-crossings provide timing information for pre- cision speed control. the L6238S contains features that offer flexible control over the start-up procedure. either the on- board auto-start algorithm can be used to control the start-up sequence or more sophisticated ex- tenal start-up algorithms can be developed using the serial port and key control/sense functions brought out to pins. 3.2 auto-start algorithm when initially powered up, the controller defaults to the internal autostart mode. when run/brake is low, the L6238S is in brake mode, and the auto-start algorithm is reset. in the brake mode, all of the lower dmos drivers are on, and the up- per drivers are off. the auto-start algorithm is based on an align & go approach and can be visualized by referring to figure 3-1. shown are the run/brake control sig- nals, sequencer function, and the three output voltage waveforms. referring to figure 3-1, the following is the se- quence of events during auto-start: with output enable =1, run/brake =0 - state machine is set to state 1 with the drivers trisatted . alignment phase (1) run/brake =1 - output stage is sequenced to state 2 and the drivers energized with output a high and output c low for 64/falign seconds. alignment phase (2) - output stage is double sequenced to state 4 with output b high and output a low for state 2 a=high b=float c=low state 4 a=low b=high c=float state 6 a=float b=low c=high 500ms/div * falign=90hz a out 1 10v b out 2 10v c out 3 10v alignment go double increments *0.711s *2.133s run/brake sequencer d95in314 figure 3-1: align+go L6238S 13/31
192/falign seconds. - during the alignment phase, the seq incre- ment signal is ignored. go phase - the internal sequencer double increments the output stage to state 6, which should produce torque in the desired direction. - with seq increment held low, the se- quencer is now controlled by the bemf zero crossings, and the motor should ramp up to speed. 3.3 externally controlled start-up algorithms enhanced start-up algorithms can be achieved by using a m processor to interact with the L6238S.' the L6238S has the ability to transition to closed loop start-up at very low speeds, re- ducing the uprocessor task to monitoring status rather than real time interaction. thus, it is a per- fect application for an existing m processor. the following control and status signals allow for very flexible algorithm development: seq_incr a low to high transition at this input is used to increment the state of the power out- put stage. it is useful during start-up, because the m processor can cycle to any desired state, or cycle through the states at any desired rate. when held high, it inhibits the bemf zero crossings from incrementing the internal se- quencer. spin sense this output is low until the first detected bemf zero crossing occurs. it then toggles at each successive zero crossing. this signal serves as a motion detector and gives useful timing information as well as the slope of the bemf. 3.4 start up approaches align & go approach the align & go approach provides a very time efficient algorithm by ener- gizing the coils to align the rotor and stator to a known phase. this approach can be achieved via the sequencing seq incr. spin sense can be monitored to assure that motion occurred. once ample time is given for alignment to occur, seq incr can be double incremented, and the spin sense pin can be monitored to detect motion. when seq incr is pulled low, control is trans- ferred to the internal sequencer, and the L6238S finishes the spinup operation. if no motion is de- tected, seq incr can be incremented to a differ- ent phase and the process can be repeated. the alignment phase may cause backward rotation, which on the average will be greater than the stepper motor approach. the auto-start algorithm described earlier is an align & go approach. the main advantages of the integrated auto-start are that the m p is not in- volved real-time, and there are a minimum of in- terface pins required to the spindle control sys- tem. stepper motor approach this approach mini- mizes backward rotation by sequencing seq incr at an initial rate that the rotor can follow. thus, it is driven in a similar fashion to a stepper motor. the rate is continually increased until the bemf voltage is large enough to reliably use the zero-crossings for commutation timing. seq incr is held low, causing control to be passed to the L6238S's internal sequencer as in the align & go approach. the stepper motor approach takes longer than the align & go approach because the initial com- mutation frequency and subsequent ramp rate must be low enough so that the motor can follow without slipping. this implies that to have a reli- able algorithm, the initial frequency and ramp rate must be chosen for the worst case motor under worst case conditions. 4.0 motor driver 4.1 output stage the output stage forms a 3-phasefull wave bridge consisting of six power dmos fet high output currents are allowed for bbrief periods. high out- put currents are allowed for brief periods. output power exceeding the stand-alone power dissipa- tion capabilities of the L6238S can be increased with the addition of an external p-fet or by the use of pulse-width-modulation. table 4-1 is a reference diagram that lists the pa- rameters associated with 8-pole motors operating at 3600 and 5400 rpm. figure 4-1 represents the waveforms associated with the output stage. the upper portion of figure 4-1 shows the flow of current in the motor wind- ings for each of the 24 phase increments. a rota- tional degree index is shown as a reference along with a base line to indicate the occurrence of a zero crosing. the output waveforms are a digitally reproduced voltage signals as measured on sam- ples.the feedback input is multiplexed between the internal bemf zero crossing detector and an externally provided sync pulse (ext index) shown in figure 10 is the classical state diagram for a phase detector along with waveform exam- ples. a typical sequence starts when the outputs switch states. referring to figure 4-1, during phase 1, output a goes high, while outputb is low. during this phase, output c is floating, and the bemf is monitored. the outputs remain in this state for 60 electrical degrees as indicated by the first set of dashed lines. after this period the out- L6238S 14/31
table 4-1 rotational speed 3600rpm 5400rpm rotational frequency 60hz 90hz rotational period 16.667ms 11.111ms electrical period 4.167ms 2.778ms phase period 694.5 m s 463.0 figure 4-1: waveforms L6238S 15/31
put switched to phase 2 with output a high and c low with the bemf amplifier monitoring output b. in order to prevent commutation current noise be- ing detectedm as a false zero crossing, a mask- ing circuit automatically blanks out all incoming signals as soon as a zero crossing is detected. when the next commutation occurs an internal counter starts counting down to set the time that the masking pulse remains. the counter is initially loaded with a number that is equal to time that is always 25% of the previous phase period or 15 electrical degrees. the time- out of the masking pulse shown for reference at the bottom of figure 4-1. thus the actual masking period is the total of the time from the detected zero crossing to the phase commutation, plus 25% of the previous period. the mask pulse op- eration is further discussed in section 4.6, slew rate control and pwm operation. after the masking period, the bemf voltage at out- put b is monitored for a zero crossing. upon de- tection of the crossing, the output is commutated after the selected phase delay insuring maximum torque. the spin sense waveform at the bottom of the figure indicates that this output signal toggles with each zero crossing. 4.2 brake delay when run/brake is brought low, a brake is initi- ated. referring to figure 4-2, sw1 is opened and the brake delay capacitor, c brake , is allowed to discharge towards groun via r brake . at the same time, switches sw2 through sw7 bring the gates of the output fets to ground halt- ing conduction, causing the motor to coast. while the motor is coasting, the bemf is used to park the heads. when cbrake reaches a voltage that is below the turn on threshold of q1, switches sw8, 9, and 10 bring the gates of the lower driv- ers to v brake potential. this enables the lower fets causing a braking action. the analog and logic supplies are not monitored in the L6238S, since the l6244 already monitors this voltage and initiates a park function when either supply drops to a predeterminated level. figure 4-2 L6238S 16/31
4.3 charge pump the charge pump circuitry is used as a means of doubling the analog supply voltage in order to al- low the upper n-channel dmos transistors to be driven like p-channel devices. the energy stored in the reservoir capacitor is also used to drive the lower drivers in a brake mode if the analog supply is lost. figure 4-3 is a simplified schematioc of the charge pump circuitry. a capacitor, c pump , is used to retrieve energy from the analog supply and then opumpso it into the storage capacitor, c resvr . an internal 300khz oscillator first turns on q2 to quickly charge c pump to approximately the rail voltage. the oscillator then turns on q1 while turning off q2. since the bottom plate of c pump , is now effectively at the rail voltage via d2. a zener-referenced series-pass regulator supplies figure 4-3 i1 islew v pump sw2 1 0 cfet upper a + - a2 vctrl x4 a3 vpower i2 islew sw3 1 0 cfet output bc outa l1 l2 l3 q1 q2 r s 3.1v slew rate reference current q3 q4 q5 r slw rsense csa pwm slew/rc lower a d95in315 vanalog figure 4-4 L6238S 17/31
a voltage, v brake , during brake mode. the maximum capacitance specified for the stor- age capacitor is 4.7 m f.for applications requiring a larger value, an external diode should be con- nected between vanalog and the storage ca- pacitor to prevent excessive inrush current from damaging the charge pump circuitry. a small value resistor (i.e. 50w) may instead be inserted in series with the storage capacitor to limit the in- rush current. 4.4 linear motor current control the output current is controlled in a linear fashion via a transconductance loop. referring to figure 4-4 the sourcing fet of one phase is forced into full conduction by connecting the gate to v pump , while the sinking transistor of an appropriate phase operates as a transconductance element. to understand the current control loop, it will be assumed that q2 in figure 4-4 is enabled via sw3 by the sequencer. during a run condition, the cur- rent in q2 is monitored by a resistor r s connected to the r sense input. the resulting voltage that appears across r s is amplified by a factor of four by a3 and is sent to a2 where it is compared to the current command signal. a2 provides sufficient drive to q2 in order to maintain the motor speed at the proper level as commanded by the speed controller. 4.5 transconductance loop stability the rc network connected to the compensation pin provides for a single pole/zero compensation scheme. the pole/zero compensation scheme. the pole/zero locations are adjusted such that a few db of gain (typ. 20db) remains in the tran- sconductance loop at frequencies higher than the zero. the inductive characteristic of the load provides the pole necessary for loop stability. thus the loop bandwidth is actually limited by the motor it- self. figure 4-5 shows the complete transconductance loop including compensation, plus the response. the bode plot depicts the normal way to achieve stability in the loop. the pole andzero are used to set a gain of 20db at a higher frequency and the pole of the motor cuts the gain to achieve stabil- ity. loop instability may be caused by two factors: 1)the motor pole is too close to the zero. refer- ring to figure 4.6, the zero is not able to dec- rement the shift of phase, and when the effect of the pole is present, the phase shift may reach 180 and the loop will oscillate. to rec- tify this situation, the pole/zero must be shifted at lower frequencies by increasing the compensation capacitor. figure 4-5 figure 4-6 figure 4-7 L6238S 18/31
2)the motor capacitance, cm, itself can inter- fere with the loop, creating double poles. if the gain at higher frequencies is sufficiently high, the double pole slope of 40db/decade can cause the phase shift to reach 180 , re sulting in oscillation. figure 4-8 is a bode plot showing how to correct this situation. the bold line indicates the response with relatively high gain at the higher frequencies. by leaving the pole unchanged and increasing the zero, the response indicated by the dashed lines can be achieved. 4.6 slew rate control a 3-phase motor appears as an inductive load to the power supply. the power supply sees a dis- turbance when one motor phase turns off and another turns on because the fet turn-off time is much shorter than the l/r rise time. abrupt fet turn-off without a proper snubbing circuit can even cause current recirculation back into the supply. however, the need for a snubber circuit can be eliminated by controlling the turn-off time of the fets. the rate at which the upper and lower drivers turn off is programmable via an external resistor, s slew connected to the slew rate pin. this re- sistor defines an internal current source that is utilized to limit the voltage slew rate at the outputs during transition, thus minimizing the load change that the power supply sees. to insure proper operation the range of resistor values indicated should not be exceeded and in some applications values near the end points should be avoided as discussed below. low values of rslew - if a relatively low value of rslew is selected, the resultant fast slew rate will result in increased commutation cross-over cur- rent, higher emi, and large amount of commuta- tion current. this last case can cause voltage spikes at the output that can go as much as lv below ground level. this situation must be avoided in this inte- grated circuit (as in most) since it causes unpre- dictable operation. high values of rslew - higher values of rslew result of course in slow slew rates at the outputs which is, under most conditions, the desired case since the problems associated with fast rates are reduced. the additional advantage is lower acoustical noise. problems can occur though if the slew rate for a figure 4-8 figure 4-9: effect of slow slew rate. L6238S 19/31
given application is too slow. figure 4-9 is an os- cillograph taken on a device that had a fairly large value for rslew and failed to spin up and phase lock a motor. the problem manifests itself as the motor begins to spin up. at lower rpms, the bemf of the motor is relatively small resulting in higher amounts of commutation current. in figure 4-9, the upper waveform is the voltage appearing at output relative to the center tap input. the lower waveform is the actual output of the bemf ampli- fier available on special engineering prototypes. the oscillograph was taken just as the problem occured. the period between zero crossings was ~800 m s resulting in a mask time period of 200 m s. as can be seen, the excessively long slew rate actually exceeded the mask period and was de- tected as a zero crossing. this resulted in improper sequencing of the out- puts relative to the proper phases and caused the motor to spin down. 4.7 ext pfet driver the power handling capabilities of the 3 phase output stage can be extended with the addition of a single p-channel fet. figure 4-10 shows the ext fet connection and demonstrates how the L6238S automatically senses the fets presence. when the voltage at the gate drive pin is 0.7v, the output of com- parator a3 goes high, removing the variable drive a1 from the internal fets and connects them in- stead to vanalog via the commutation switches to facilitate full conduction. the upper fets drive paths are not shown for clarity. a3 also closes sw2 allowing a1 to linearly drive the external p-channel fet q1 via inverter a2. 4.8 bemf ampolifier since no hall effect sensors are required, the commutation information is derived from the bemf voltage zero-crossings of the undriven phase with respect to the center tap. the bemf comparator and associated signal levels are depicted in figure 4-11. for reliable operation, the bemf signal am- plitude should be a minimum of 60 mv to be properly detected. in order to provide for noise immunity, internal hysteresis is incorporated in the detection circuitry to prevent false zero cross- ing detection. for laboratory evaluation purposes, a simple re- figure 4-10: external p-fet. L6238S 20/31
sistive network as shown in figure 4.12 can be used to emulate the bemf of the motor. the actual bemf zero-crossing is 30 electrical de- grees (50% of a commutation interval) away from the optimal switch point. a digital counter circuit measures 50% of the previous interval to deter- mine the next interval's commutation delay from the zero crossing. during the low rpm stages of start up the long commutation intervals may cause the counter to overflow, in which case 50% of the max count will be less than 50% of the ideal commutation interval. therefore, the torque will not be optimal until the desired commutation interval is less than the dynamic range of the counter. 4.9 center tap protection spindle motors with a high number of windings exhibit a transformer coupling effect that in some cases can cause relatively high currents to flow through the center tap input. current flowing out of the center tap pin as high as 25ma has been observed with certain motors. figure 4-12: bemf emulator r1 1k ds1 to center tap input d95in317 figure 4-13 figure 4-11: bemf amplifier. vo bemf -35 -25 0 25 35 vi bemf(mv) slope=0 slope=1 d95in316 L6238S 21/31
the high current flows from the grounded sub- strate of the integrated circuit (p-type material), through one or more epitaxial pockets (n-type ma- terial) and out the center par pin. this current can cause adverse operation of the controllet due to substrate injection and might possibility damage the internal metalization runs. the normal current for this input is in the 200 m a range. referring to figure 4-13, a simple protection scheme consisting of a 1k resistor and a low cur- rent schottky diode should be added if the appli- cation causes excessive current (i.e. >1ma) to flow through the center tap pin. 5.0 pwm motor current control a unique feature of the L6238S in the optional pulse width modulation (pwm) control of motor current. using variable-frequency, constant-off time current-mode control, the L6238S can drive higher power motors without the need for external drivers, while minimizing internal power dissipa- tion. additional benefits include reduced power supply consumption (up to 50% savings) and lower watt- age requirements for the current sensing resistor. constant-off time current-mode control, oper- ates on the principle of monitoring the motor cur- rent and comparison it to a reference or control level. when the motor current reaches this commanded level, the output drivers turn off and remain off for a constant-off time. after this off time the drivers turn back on to repeat the cycle. figure 5.1 is a block diagram of the pwm control circuitry. when using pwm as opposed to linear control, two changes are made to the control loop: 1.the slew rate control is disabled, allowing the outputs to slew at a minimum rate of 10v/ m s. this is accomplished by closing sw3 and sw5. 2.the ota amplifier is taken out of the control loop via sw6. the lower drivers are now driven into hard conduction by tying the gates to the analog supply during the on time of the pwm cycle. the current in the motor windings is monitored via the voltage dropped in the sensing resistor, r sense . this voltage is multiplied by a factor of 4 in the current sense amplifier (csa) and sent to nega- tive input of the pwm comparator (a2). the control voltage, v control , is applied to the posi- tive input of a2. when the output of the csa reaches a level that is equal to the commanded level, the output of a2 switches low, toggling the latch comprised of n1 and n2. this causes the upper drivers to turn off and opens sw1. q3 turns off allowing the constant-off time capacitors, i1 islew v pump sw2 1 0 cfet upper a + - a1 pwm/slew x4 a3 vpower i2 islew sw3 1 0 cfet output bc outa l1 l2 l3 q4 q5 slew rate reference current r slw rsense csa vctrl lower a d95in318 n3 q1 q2 vanalog 3.1v sw1 q3 1.2v sw5 n1 sw4 n2 a2 + - pwm/lin control 1 0 from trans. loop csa sw6 v analog coff rslew figure 5-1 L6238S 22/31
c off to discharge to dischargte through r slew , initi- ating the constant-off time-out. when the volt- age on c off reaches 1.2v, comparator a1switches state toggling the latch in the opposite state, turn- ing the upper driver back on. sw1 also closed quickly charging up c off for the next cycle. 5.1 pwm design considerations in order to select the parameters associated with pwm operation, the following factors must be taken into consideration: 1. pwm switching frequency 2. duty cycle 3. motor currents 4. minimum on time 5. noise blanking 6. bemf masking/sampling 5.1.1. pwm switching frequency the pwm switching frequency f pwm is found from: f pwm = 1 t on + t off (5.1.1) where: t on = the time required for the motor current to reach the commanded level. t off = the programmed off time. the two main considerations for this parameter are the minimum and maximum switching fre- quency. the maximum switching frequency occurs during the start-up and should be kept below 50khz due tointentional bandwidth limitations and output switching losses. 5.1.2 duty cycle besides reducing the power dissipation of the controller output stage, running in pwm offers 2 additional ofreeo benefits: a. reduced powe supply current at start up b. lower power rating for the motor current sense resistor. figure 5-2 is the current path during the on time of a phase period. the current from the supply passes through the upper sourcing dmos, q3 transistor through the two driven winding, the lower dmos, q2 and finally through the current sensing resistor r sns . since both q3 and q4 are on, while q3 is turned off. the voltage, causing the current to continue to flow through q2, and q4. if the duty cycle is nearor at 50%, then for 1/2 the pwm cycle, no current is flowing from the power supply or the sense resistor while current is still flowing in the motor. this lowers the requirement for both the power supply and the power rating for the sensing resistor. 5.1.3 motor currents note: it is not the objective of this section to describe the principles of brushless dc motor, but to provide sufficient information about the parameters associated with pwm operation in order to optimize an application. a simplified model of a motor is shown in figure 5- 4. for this discussion, lower order effects due to mutual inductance between windings, resistance due to losses in the magnetic circuit, etc. are not shown. the motor at stall is equal to a resistance, rmtr , in series with an inductance, lmtr . when the mo- tor is rotating, there is an induced emf that ap- pears across the armaure terminals and is shown in figure 5-4 as an internally generated voltage ibemf), eg . l1 l2 outputa outputb d2 d1 d4 d3 q1 q2 q3 q4 v power r sense r sns d95in319 figure 5-2 l1 l2 outputa outputb d2 d1 d4 d3 q1 q2 q3 q4 v power r sense r sns d95in320 figure 5-3 L6238S 23/31
the relation between these variables is given by: v = l mtr di mtr dt r mtr i mtr + e g (5.1.2) where: v = applied voltage i mtr = motor current l mtr = total inductance of the motor windings r mtr = resistance in series with the motor e g = the internally generated voltage of the motor, proportional to the motor velocity since: e g =k e w (5.1.3) the above equations can be combined to form the basic electrical equation for a motor: v = l mtr di mtr dt r mtr i mtr + k e w (5.1.4) figure 5.5 is a simplified electrical equivalent of the output stage of the L6238S along with the model of the motor during the time that the out- put drives are conducting. the additional resistance associated with the out- put stage and sensing resistor are also in series with the motor. if we let r s equal the total series resistence: r s = 2*r dson +r mtr +r sense (5.1.5) then (5.1.4) becomes: v = l mtr di mtr dt r s i mtr + e g (5.1.6) figure 5-6 is an equivalent circuit of the output stage during the constant-off period. during the off time the lower driver for the particular phase beign driven remains on. the internally generated voltage forces the path of current though the motor, its series resistance, the rdson of the lower driver and finally through the opposite lower driver. pwm example (refer to figure 5-7) the following is an example on how to select the timing parameters. given: dcstart current = 1.25a ripple current = 100ma duty cycle = 50% motor interface (l) = 880 m h total series resistance (r s ) = 4.8 w if the worst case start current is 1.25a and the duty cycle is 50%, then the peak current, it will be: i t = 1.25 + 0.1 2 i t = 1.30a eg + - rmtr lmtr d95in321 figure 5-4 + - rmtr lmtr d95in322 upper rdson kew lower rdson rsense figure 5-5 + - rmtr lmtr d95in323 kew lower rdson lower rdson figure 5-6 L6238S 24/31
the valley current, i b will thereforebe: i b = 1.30 - 0.1a i b = 1.20a during the align and go phase (where the power dissipation requirements are highest, eg is zero. the initial time required to reach the peak current is: t init = l r ln ? ? ? 1 i,r v ? ? ? (5.1.7) substituting values: t init = 880e 6 4.8 ln ? ? ? 1 1.3 ? 4.8 12 ? ? ? t init = 134.6 m s the on time can be calculated from: t on = l r s ln ? ? ? ? ? ? ? v r s i b v r s i t ? ? ? ? ? ? ? (5.1.8) substituting values: t on = 880e 6 4.8 ln ? ? ? ? ? ? ? 12 4.8 1.2 12 4.8 1.3 ? ? ? ? ? ? ? t on = 14.67 m s during the off time, the motor current continues to flow through the dmos transistors and threfore the voltage drop remains constant across the windings. the time required for the inductor current to reach the valley current is given by: t off = l r ln ? ? ? i t i b ? ? ? (5.1.9) substituting values: t off = 880e 6 4.8 ln ? ? ? 1.3 1.2 ? ? ? t off = 14.67 m s note: that the parameters for this example were selected to arrive at a 50% duty cycle. this will not always be the case due to factors such as fixed motor parameters, etc. the constant off timer period can be determined from: t off = r slew ? c off ? ln ? ? ? v chrg v trip ? ? ? (5.1.10) where: t off = constant-off time r slew = slew rate resistor c off = off time capacitor v chrg = initial capacitor charge voltage v trip = capacitor lower trip threshold substituting nominal values given: t off = 0.75 ? r slew ? c off solving for c off c off = t off 0.75r slew in the example, to set the off timer for a 50% duty cycle: given: t off = 14.67 m s r slew = 100k w (typical value) c off = 14.67e 6 100e 3 c off 146pf 5.1.4 minimum on time the bandwidth of the pwm loop was optimized to reject unwanted switching noise while providing 20 m s/div iout a 200ma d95in324 4 it=1.3a ib=1.2a iavg=1.25a figure 5-7 L6238S 25/31
sufficient response, commensurate with the switching speed of the output drivers. at higher frequencies the switching losses inherent in the drivers start to negative any of the power dissipa- tion savings gained with pwm operation. the current sense amplifier has a minimum slew rate of 0.31v/ m s. with a worst case motor peak start-up current of 2.5a and sense resistor of 0.33, the resultant r sense voltage would be equal to 825mv. with a minimum gain of 3.8v/v, the csa output voltage would have to slew to 3.14v. therefore it would require approximately 10 m s for the output voltage to reach the required com- manded level. if an on time were selected that was less than this time, the motor current would overshoot the desired level resulting in incorrect current control possibly exceeding the output capabilities of the drivers. 5.1.5 noise blanking referring to figure 5-8, when operating with lower levels of current (i.e. < 700ma, with rsense = 0.33 w ), the possibility exiss where the noise due to output turn-on can exceed the com- manded current level causing prematire turn- off. in order to provide noise immunity from this switching noise, a blanking circuit automatically rejects any signal appearing at the output of the csa for a 3 m s period. figure 5-9 is an additional block diagram of the pwm control loop including the noise blanking cir- cuit. the output of a3 goes high when ever the voltage at the csa input is more positive then the control voltage. this is the case when either the motor current or the turn-on transient has reached the com- manded level. the output of a3 is gates by n11. in order to provide a blanking period, q1 is turned 10 m s/div vrsense d95in325 1 3 m s blanking pulse commanded current level figure 5-8 c1 8pf q1 n6 n10 i1 5 m a n1 delay to ouput drivers n7 n8 n11 n9 n12 2.4v sw1 a2 + - 1.2v a3 + - n4 n2 n3 clk_bemf n5 i2 20 m a q2 x4 pwm/lin run/brake n12 q3 pwm timer c4 pwm comp vcontrol csa input pwm_slew c3 r1 d95in326 figure 5-9 L6238S 26/31
on during the constant-off time, charging c1 to the internal rail. at the end of the off time, q1 is turned off allowing current source i1 to dis- charge the capacitor towards ground. while the voltage on c1 is above the low input threshold of n1, the output of n1 is low, preventing any change of state at the output of n11 due to a high a3 output. when the capacitor reaches the low in- put threshold of n1, n1 chnges state allowing a3 to control the state of n11. 5.1.6 masking/bemf sampling in pwm the method of sampling the floating phase for the bemf zero crossing defers between linear and pwm operation. in linear mode, the bemf is sam- pled continuously after the mask time-out, until the zero crossing is detected. then the mask is enabled for a time based on the commutation phase delay plus the additional time based on the previous period as explained earlier. with pwm operation however, the switching noise at turn on (after the constant-off time) can be significant, especially at low rpms where the bemf is the lowest. in order to provide the greatest noise immunity in pwm, the floating phase is monitored only at the point where the output is about to be turned off. in operation, when the motor current reaches the commanded level, the floating phase is first moni- tored to determine if the bemf has crossed the zero. the output is then turned off for the con- stant-off time out. as the motor current increases through, the in- creasing bemf causes the motor current to natu- rally decrease. eventually a point is reached where the pwm is running at 100% duty cycle and the motor current cannot reach the com- manded level. at this time the bemf is no longer smpled, preventing further commutation of the output. the pwm limit timer is used to set up a maxi- mum on time. when this limit is exceeded the method of sensing the bemf is essentially the same as in the case of operating in linear mode. figure 5-10 is an oscillograph of the controller op- erating in pwm mode. the top trace is a out . the 2nd trace is the voltage seen at the pwm/slew pin indicating the exponential discharging of the timing capacitor during the off time. trace 3 is the voltage appearing on the pwm timer capaci- tor, while trace 4 is the motor current. referring again to figure 5-9, and 5-10 transistor q2 is turned on at the beginning of the off time, discharging the external capacitor c4 to near ground level. at the end of the off-time, q2 is turned off and c4 starts charging linearly via i2. c4 is again discharged at the beginning of the off time and the cycle repeats. as long as c4 does not reach the threshold of a1 (typically 3.5v), the bemf is only sampled just before turn- off of the output. as the motor is starting up in fig- ure 5-10, the duty cycle is roughly 50%. the pwm limit timer is reset to ground by the start of the off timer before reaching the 3.5v threshold. in figure 5-11, as the motor spins up, the on time of the output increases and the pwm limit timer reaches the 3.5v. eventually the duty cycle reaches 100% and the sampling of the bemf is essentially the same as in the linear mode. the selection of components for the pwm timer is not critical. since the objective is to sample the bemf only at turn off to maximize the signal to noise ratio, the pwm timer slope can be set up to convert to the full bemf sampling after a few revo- lutions of the motor when the bemf has reached an appropriatevoltage output. 20 m s/div 4 1a iout a aout d95in327 fpwm=50khz coff=120pf ctmr=220pf 3 500mv 2 2v pwm/slew 1 10v pwm limit timer figure 5-10 50 m s/div 4 aout iout a d95in328 fpwm=12khz coff=120pf ctmr=220pf 3 500mv 2 2v pwm/slew 1 10v pwm limit timer 1a figure 5-11 L6238S 27/31
plcc44 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 L6238S 28/31
a a2 a1 b seating plane c 11 12 22 23 33 34 44 e3 d3 e1 e d1 d e 1 k b pqfp44 l l1 0.10mm .004 pqfp44 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.35 0.50 0.0138 0.0197 c 0.13 0.23 0.005 0.009 d 16.95 17.20 17.45 0.667 0.677 0.687 d1 13.90 14.00 14.10 0.547 0.551 0.555 d3 10.00 0.394 e 1.00 0.039 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 10.00 0.394 l 0.65 0.80 0.95 0.026 0.0315 0.0374 l1 1.60 0.063 k 0 (min.), 7 (max.) L6238S 29/31
a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b t q f p6 4 l l1 seating plane 0.10mm tqfp64 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) L6238S 30/31
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs- thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics printed in italy all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. L6238S 31/31

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